1. Field of the Invention
This invention generally relates to a third-order sigma-delta analog-to-digital converter and, more particularly, to a third-order sigma-delta oversampled analog-to-digital converter network with low sensitivity component mismatch and finite amplifier gain.
2. General Description of the Prior Art
High resolution analog-to-digital (or A/D) signal conversion can be achieved with lower resolution components through the use of oversampled interpolative (or sigma-delta) modulation followed by digital low pass filtering and decimation. Oversampling refers to operation of the modulator at a rate many times above the signal Nyquist rate, whereas decimation refers to reduction of the clock rate down to the Nyquist rate.
Sigma delta modulators (sometimes referred to as delta sigma modulators) have been used in analog-to-digital converters for some time. Detailed general information can be obtained from the following technical articles which are hereby incorporated by reference.
1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", J. C. Candy, IEEE Transactions on Communications, Vol. COM-22, No. 3, pp. 298-305, March 1974 PA0 2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", J. C. Candy, et al., IEEE Transactions on Communications, Vol. COM-24, No. 11, pp. 1268-1275, November 1976 PA0 3) "A Use of Double Integration in Sigma Delta Modulation", J. C. Candy, IEEE Transactions on Communications, Vol. COM-33, No. 3, pp. 249-258, March 1985.
Substantial effort has been expended in the field of oversampled analog-to-digital converter design to develop plural-order sigma-delta modulators in order to obtain higher resolution for a given oversampling ratio. As the term "order" is used herein, the order of a sigma-delta modulator is determined directly by how many times the error between its output and input signals is integrated with respect to time, while the order of a sigma-delta converter stage within a plural-stage sigma-delta A/D converter is determined directly by how many times the input signal to that stage is integrated with respect to time in reaching the output connection of that stage.
In the above type of analog-to-digital converter, resolution is predominantly governed by two factors: (1) the ratio of the modulator clock to the Nyquist rate, henceforth referred to as the oversampling ratio, and (2) the "order" of the modulator. "Order" in this context is analogous to the order of a frequency selective filter and indicates the relative degree of spectral shaping that is provided by the modulator. As with a filter, higher selectivity is obtainable with a higher order at the expense of increased hardware complexity. In recognition of these two factors, recent implementations of high resolution oversampled analog-to-digital converters have employed both large oversampling ratios and high modulator order. However, practical considerations can limit the extent to which oversampling rate and modulator order can be taken. For instance, for a given modulator clock rate, the oversampling ratio is inversely proportional to the Nyquist rate after decimation and thus cannot be made arbitrarily high without sacrificing conversion rate. Different considerations set bounds on the modulator order. Implementations of order greater than two, using a single quantizer, can be shown to be only conditionally stable and are therefore not viable.
An alternative approach can be used to effectively provide high order noise shaping with cascaded low-order modulators to ensure stable operation. Unfortunately, the matching of the modulators in such structure is crucial, and the degree of mismatch governs accuracy of the overall converter. Requirements of close component matching and high operational amplifier (or "op amp") gains imply that such circuit can only be manufactured with a low yield, and possibly will require trimming, thereby being expensive to produce.
Early work in this field has been directed at implementation of modulators of first and second order, due to the stability concerns associated with orders of three or greater. T. Hayashi et al., in "A Multistage Delta-Sigma Modulator Without Double Integrator Loop", Proc. IEEE 1986 Int. Solid-State Circuits Conf., pp. 182-183, February 1986, describe an approach in which second-order performance is obtained using a cascade connection of two first-order stages. The quantization error of the first stage is supplied to the second stage so that the second stage output signal, after a digital differentiation, contains a replica of the frequency-shaped quantization noise. Finally, a subtraction of the second stage output signal from that of the first stage yields a signal that contains only the quantization noise of the second stage with second-order noise-shaping. However, this method requires tight matching of the characteristics of the two first-order modulators and high op amp gains. Furthermore, there is a strong desire to employ a third-order modulator in which first- and second-order quantization noise do not accompany the digital output signal generated by the oversampling analog-to-digital converter network.
An extension of the Hayashi et al approach to third-order analog-to-digital converter networks using a triple cascade connection of first-order modulators is described by Y. Matsuya et al. in "A 16-Bit Oversampling A-D Conversion Technology Using Triple Integration Noise Shaping", IEEE J. Solid-State Circuits, Vol. SC-22, No. 6, pp. 921-929, December 1987. However, this approach requires even tighter component matching and also requires high op amp gains in order to achieve the theoretically obtainable resolution.
A slightly different approach is disclosed by L. Longo and M. A. Copeland in "A 13-Bit ISDN-Band ADC Using Two-Stage Third Order Noise Shaping", Proc. 1988 Custom Integrated Circuit Conf., pp. 21.2.1-4, June 1988, wherein a second-order modulator is connected in cascade with a first-order modulator to implement third-order noise-shaping. This approach has the advantage of reducing the component matching requirements somewhat from the other implementations.
An improved third-order sigma-delta analog-to-digital converter which achieves third-order noise-shaping with reduced sensitivity to component mismatching, finite amplifier gain and other nonideal circuit attributes, herein referred to as "nonidealities" was sought by the present inventor. Improved architectures for third-order sigma-delta analog-to-digital converters which can be implemented as sampled data switched- capacitor circuits were sought by the present inventor. The present inventor also sought to provide third-order quantization noise-shaping in a third-order sigma-delta analog-to-digital converter with a modulator network architecture that employs amplifiers of finite gain and is relatively insensitive to normal circuit nonidealities so that A/D converter resolution approaching the theoretical limits can be obtained.
A new third-order sigma-delta analog-to-digital converter network has been developed by the present inventor that exhibits significantly reduced sensitivity to the practical nonidealities that normally limit resolution of prior-art third-order sigma-delta analog-to-digital converter networks, i.e., component mismatching, amplifier non-linearity, finite gain, excessive settling time, and limited signal dynamic range. Thorough simulations, taking into account nonidealities, indicate that 16-bit resolution at an 80 kHz conversion rate is achievable with the new A/D converter network operated at an oversampling ratio of 64. This performance is attainable despite component matching of only 2% and op amp gains as low as 1000. The realization of these performance levels despite only modest required circuit specifications indicate that a low cost, highly manufacturable A/D converter network is now practicable. MOS, CMOS, BiCMOS, GaAs. or Bipolar integrated circuit technologies can be used with this new A/D converter network to implement a completely monolithic A/D converter network with no external components other than decoupling capacitors.